
2010 Microchip Technology Inc.
Preliminary
DS39964B-page 471
PIC18F47J53 FAMILY
BRA
Unconditional Branch
Syntax:
BRA
n
Operands:
-1024
n 1023
Operation:
(PC) + 2 + 2n
PC
Status Affected:
None
Encoding:
1101
0nnn
nnnn
Description:
Add the 2’s complement number ‘2n’ to
the PC. Since the PC will have
incremented to fetch the next
instruction, the new address will be
PC + 2 + 2n. This instruction is a
two-cycle instruction.
Words:
1
Cycles:
2
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read literal
‘n’
Process
Data
Write to
PC
No
operation
No
operation
No
operation
No
operation
Example:
HERE
BRA
Jump
Before Instruction
PC
=
address (HERE)
After Instruction
PC
=
address (Jump)
BSF
Bit Set f
Syntax:
BSF
f, b {,a}
Operands:
0
f 255
0
b 7
a
[0,1]
Operation:
1 f<b>
Status Affected:
None
Encoding:
1000
bbba
ffff
Description:
Bit ‘b’ in register ‘f’ is set.
If ‘a’ is ‘0’, the Access Bank is selected.
If ‘a’ is ‘1’, the BSR is used to select the
GPR bank (default).
If ‘a’ is ‘0’ and the extended instruction
set is enabled, this instruction operates
in Indexed Literal Offset Addressing
mode whenever f
95 (5Fh). See
Words:
1
Cycles:
1
Q Cycle Activity:
Q1
Q2
Q3
Q4
Decode
Read
register ‘f’
Process
Data
Write
register ‘f’
Example:
BSF
FLAG_REG, 7, 1
Before Instruction
FLAG_REG
=
0Ah
After Instruction
FLAG_REG
=
8Ah